#ifndef HW_INTS_H
#define HW_INTS_H

//*****************************************************************************
//
// PIE Interrupt Numbers
// 0x00FF = PIE Table Row
// 0xFF00 = PIE Table Column
//
//*****************************************************************************

#define INT_RTOS      0x0101 // 1.1 - RTOS Interrupt
#define INT_ADCA1     0x0102 // 1.2 - ADCA Interrupt 1
#define INT_ADCB1     0x0103 // 1.3 - ADCB Interrupt 1
#define INT_ADCC1     0x0104 // 1.4 - ADCC Interrupt 1
#define INT_XINT1     0x0105 // 1.5 - XINT1 Interrupt
#define INT_XINT2     0x0106 // 1.6 - XINT2 Interrupt
#define INT_TIMER0    0x0107 // 1.7 - Timer 0 Interrupt
#define INT_WAKE      0x0108 // 1.8 - Halt Wakeup/Watchdog Interrupt
#define INT_ADCF1     0x0109 // 1.9 - ADCF Interrupt 1
#define INT_ADCF2     0x0109 // 1.10 - ADCF Interrupt 2
#define INT_SYS_ERR   0x010A // 1.11 - SYS ERROR Interrupt
#define INT_BGCCRC    0x010A // 1.11 - BGCRC Interrupt
#define INT_ECATSYNC0 0x010B // 1.11 - ETHCAT SYNC 0 Interrupt
#define INT_ECAT      0x010C // 1.12 - ETHCAT Interrupt
#define INT_CIPC0     0x010D // 1.13 - CIPC 0 Interrupt
#define INT_CIPC1     0x010E // 1.14 - CIPC 1 Interrupt
#define INT_CIPC2     0x010F // 1.15 - CIPC 2 Interrupt
#define INT_CIPC3     0x0110 // 1.16 - CIPC 3 Interrupt

#define INT_EPWM1_TZ  0x0201 // 2.1 - ePWM1 Trip Zone Interrupt
#define INT_EPWM2_TZ  0x0202 // 2.2 - ePWM2 Trip Zone Interrupt
#define INT_EPWM3_TZ  0x0203 // 2.3 - ePWM3 Trip Zone Interrupt
#define INT_EPWM4_TZ  0x0204 // 2.4 - ePWM4 Trip Zone Interrupt
#define INT_EPWM5_TZ  0x0205 // 2.5 - ePWM5 Trip Zone Interrupt
#define INT_EPWM6_TZ  0x0206 // 2.6 - ePWM6 Trip Zone Interrupt
#define INT_EPWM7_TZ  0x0207 // 2.7 - ePWM7 Trip Zone Interrupt
#define INT_EPWM8_TZ  0x0208 // 2.8 - ePWM8 Trip Zone Interrupt
#define INT_EPWM9_TZ  0x0209 // 2.9 - ePWM9 Trip Zone Interrupt
#define INT_EPWM10_TZ 0x020A // 2.10 - ePWM10 Trip Zone Interrupt
#define INT_EPWM11_TZ 0x020B // 2.11 - ePWM11 Trip Zone Interrupt
#define INT_EPWM12_TZ 0x020C // 2.12 - ePWM12 Trip Zone Interrupt
#define INT_EPWM13_TZ 0x020D // 2.13 - ePWM13 Trip Zone Interrupt
#define INT_EPWM14_TZ 0x020E // 2.14 - ePWM14 Trip Zone Interrupt
#define INT_EPWM15_TZ 0x020F // 2.15 - ePWM15 Trip Zone Interrupt
#define INT_EPWM16_TZ 0x0210 // 2.16 - ePWM16 Trip Zone Interrupt

#define INT_EPWM1  0x0301 // 3.1 - ePWM1 Interrupt
#define INT_EPWM2  0x0302 // 3.2 - ePWM2 Interrupt
#define INT_EPWM3  0x0303 // 3.3 - ePWM3 Interrupt
#define INT_EPWM4  0x0304 // 3.4 - ePWM4 Interrupt
#define INT_EPWM5  0x0305 // 3.5 - ePWM5 Interrupt
#define INT_EPWM6  0x0306 // 3.6 - ePWM6 Interrupt
#define INT_EPWM7  0x0307 // 3.7 - ePWM7 Interrupt
#define INT_EPWM8  0x0308 // 3.8 - ePWM8 Interrupt
#define INT_EPWM9  0x0309 // 3.9 - ePWM9 Interrupt
#define INT_EPWM10 0x030A // 3.10 - ePWM10 Interrupt
#define INT_EPWM11 0x030B // 3.11 - ePWM11 Interrupt
#define INT_EPWM12 0x030C // 3.12 - ePWM12 Interrupt
#define INT_EPWM13 0x030D // 3.13 - ePWM13 Interrupt
#define INT_EPWM14 0x030E // 3.14 - ePWM14 Interrupt
#define INT_EPWM15 0x030F // 3.15 - ePWM15 Interrupt
#define INT_EPWM16 0x0310 // 3.16 - ePWM16 Interrupt

#define INT_ECAP1   0x0401 // 4.1 - eCAP1 Interrupt
#define INT_ECAP2   0x0402 // 4.2 - eCAP2 Interrupt
#define INT_ECAP3   0x0403 // 4.3 - eCAP3 Interrupt
#define INT_ECAP4   0x0404 // 4.4 - eCAP4 Interrupt
#define INT_ECAP5   0x0405 // 4.5 - eCAP5 Interrupt
#define INT_ECAP6   0x0406 // 4.6 - eCAP6 Interrupt
#define INT_ECAP7   0x0407 // 4.7 - eCAP7 Interrupt
#define INT_ADCD1   0x0408 // 4.8 - ADCD1 Interrupt
#define INT_FSITXA1 0x0409 // 4.9 - FSITXA Interrupt 1
#define INT_FSITXA2 0x040A // 4.10 - FSITXA Interrupt 2
#define INT_FSITXB1 0x040B // 4.11 - FSITXB Interrupt 1
#define INT_FSITXB2 0x040C // 4.12 - FSITXB Interrupt 2
#define INT_FSIRXA1 0x040D // 4.13 - FSIRXA Interrupt 1
#define INT_FSIRXA2 0x040E // 4.14 - FSIRXA Interrupt 2
#define INT_FSIRXB1 0x040F // 4.15 - FSIRXB Interrupt 1
#define INT_FSIRXB2 0x0410 // 4.16 - FSIRXB Interrupt 2

#define INT_EQEP1     0x0501 // 5.1 - eQEP1 Interrupt
#define INT_EQEP2     0x0502 // 5.2 - eQEP2 Interrupt
#define INT_EQEP3     0x0503 // 5.3 - eQEP3 Interrupt
#define INT_EQEP4     0x0504 // 5.4 - eQEP4 Interrupt
#define INT_CLB1      0x0505 // 5.5 - CLB1 Interrupt
#define INT_CLB2      0x0506 // 5.6 - CLB2 Interrupt
#define INT_CLB3      0x0507 // 5.7 - CLB4 Interrupt
#define INT_CLB4      0x0508 // 5.8 - CLB8 Interrupt
#define INT_SDFM1     0x0509 // 5.9 - SDFM1 Interrupt
#define INT_SDFM2     0x050A // 5.10 - SDFM2 Interrupt
#define INT_ECATRST   0x050B // 5.11 - ETHCAT RST Interrupt
#define INT_ECATSYNC1 0x050C // 5.12 - ETHCAT SYNC1 Interrupt
#define INT_SDFM1DR1  0x050D // 5.13 - SDFM1DR1 Interrupt
#define INT_SDFM1DR2  0x050E // 5.14 - SDFM1DR2 Interrupt
#define INT_SDFM1DR3  0x050F // 5.15 - SDFM1DR3 Interrupt
#define INT_SDFM1DR4  0x0510 // 5.16 - SDFM1DR4 Interrupt

#define INT_SPIA_RX  0x0601 // 6.1 - SPIA Receive Interrupt
#define INT_SPIA_TX  0x0602 // 6.2 - SPIA Transmit Interrupt
#define INT_SPIB_RX  0x0603 // 6.3 - SPIB Receive Interrupt
#define INT_SPIB_TX  0x0604 // 6.4 - SPIB Transmit Interrupt
#define INT_LINA     0x0605 // 6.5 - LINA Interrupt
#define INT_ADCE1    0x0606 // 6.6 - ADCE1 Interrupt
#define INT_LINB     0x0607 // 6.7 - LINB Interrupt
#define INT_ADCE2    0x0608 // 6.8 - ADCE2 Interrupt
#define INT_SPIC_RX  0x0609 // 6.9 - SPIC Receive Interrupt
#define INT_SPIC_TX  0x060A // 6.10 - SPIC Transmit Interrupt
#define INT_SPID_RX  0x060B // 6.11 - SPID Receive Interrupt
#define INT_SPID_TX  0x060C // 6.12 - SPID Transmit Interrupt
#define INT_SDFM2DR1 0x060D // 6.13 - SDFM2DR1 Interrupt
#define INT_SDFM2DR2 0x060E // 6.14 - SDFM2DR2 Interrupt
#define INT_SDFM2DR3 0x060F // 6.15 - SDFM2DR3 Interrupt
#define INT_SDFM2DR4 0x0610 // 6.16 - SDFM2DR4 Interrupt

#define INT_DMA_CH1  0x0701 // 7.1 - DMA Channel 1 Interrupt
#define INT_DMA_CH2  0x0702 // 7.2 - DMA Channel 2 Interrupt
#define INT_DMA_CH3  0x0703 // 7.3 - DMA Channel 3 Interrupt
#define INT_DMA_CH4  0x0704 // 7.4 - DMA Channel 4 Interrupt
#define INT_DMA_CH5  0x0705 // 7.5 - DMA Channel 5 Interrupt
#define INT_DMA_CH6  0x0706 // 7.6 - DMA Channel 6 Interrupt
#define INT_EQEP5    0x0707 // 7.7 - EQEP5 Interrupt
#define INT_EQEP6    0x0708 // 7.8 - EQEP6 Interrupt
#define INT_FSIRXC1  0x0709 // 7.9 - FSIRXC Interrupt 1
#define INT_FSIRXC2  0x070A // 7.10 - FSIRXC Interrupt 2
#define INT_FSIRXD1  0x070B // 7.11 - FSIRXD Interrupt 1
#define INT_FSIRXD2  0x070C // 7.12 - FSIRXD Interrupt 2
#define INT_SDFM3DR1 0x070D // 7.13 - SDFM3DR1 Interrupt
#define INT_SDFM3DR2 0x070E // 7.14 - SDFM3DR2 Interrupt
#define INT_SDFM3DR3 0x070F // 7.15 - SDFM3DR3 Interrupt
#define INT_SDFM3DR4 0x0710 // 7.16 - SDFM3DR4 Interrupt

#define INT_I2CA      0x0801 // 8.1 - I2CA Interrupt
#define INT_I2CA_FIFO 0x0802 // 8.2 - I2CA  FIFO Interrupt
#define INT_I2CB      0x0803 // 8.3 - I2CB Interrupt
#define INT_I2CB_FIFO 0x0804 // 8.4 - I2CB  FIFO Interrupt
#define INT_UARTA     0x0805 // 8.5 - UARTA Interrupt
#define INT_UARTB     0x0806 // 8.6 - UARTB Interrupt
#define INT_EPWM17_TZ 0x0807 // 8.7 - EPWM17 TZ Interrupt
#define INT_EPWM18_TZ 0x0808 // 8.8 - EPWM18 TZ Interrupt
#define INT_ADCG4     0x0809 // 8.9 - ADCG4 Interrupt
#define INT_ADCF4     0x080A // 8.10 - ADCF4 Interrupt
#define INT_SDFM3     0x080B // 8.11 - SDFM3 Interrupt
#define INT_SDFM4     0x080C // 8.12 - SDFM4 Interrupt
#define INT_CLB5      0x080D // 8.13 - CLB5 Interrupt
#define INT_CLB6      0x080E // 8.14 - CLB6 Interrupt
#define INT_ADCE3     0x080F // 8.15 - ADCE3 Interrupt
#define INT_ADCE4     0x0810 // 8.16 - ADCE4 Interrupt

#define INT_SCIA_RX         0x0901 // 9.1 - SCIA RX Interrupt
#define INT_SCIA_TX         0x0902 // 9.2 - SCIA TX Interrupt
#define INT_SCIB_RX         0x0903 // 9.3 - SCIB RX Interrupt
#define INT_SCIB_TX         0x0904 // 9.4 - SCIB TX Interrupt
#define INT_CANA            0x0905 // 9.5 - CANA Interrupt
#define INT_ADCG_EVT        0x0906 // 9.6 - ADCG EVT Interrupt
#define INT_EPWM17          0x0907 // 9.7 - EPWM17 Interrupt
#define INT_EPWM18          0x0908 // 9.8 - EPWM18 Interrupt
#define INT_MCANA           0x0909 // 9.9 - MCANA Interrupt
#define INT_ADCG1           0x090A // 9.10 - ADCG1 Interrupt
#define INT_ADCG2           0x090B // 9.11 - ADCG2 Interrupt
#define INT_ADCG3           0x090C // 9.12 - ADCG3 Interrupt
#define INT_PMBUSA          0x090D // 9.13 - PMBUSA Interrupt
#define INT_AES_SINTREQUEST 0x090E // 9.14 - AES_SINTREQUEST Interrupt
#define INT_ADCE_EVT        0x090F // 9.15 - ADCE_EVT Interrupt
#define INT_EMIF            0x0910 // 9.16 - EMIF Interrupt

#define INT_ADCA_EVT    0x0A01 // 10.1 - ADCA Event Interrupt
#define INT_ADCA2       0x0A02 // 10.2 - ADCA Interrupt 2
#define INT_ADCA3       0x0A03 // 10.3 - ADCA Interrupt 3
#define INT_ADCA4       0x0A04 // 10.4 - ADCA Interrupt 4
#define INT_ADCB_EVT    0x0A05 // 10.5 - ADCB Event Interrupt
#define INT_ADCB2       0x0A06 // 10.6 - ADCB Interrupt 2
#define INT_ADCB3       0x0A07 // 10.7 - ADCB Interrupt 3
#define INT_ADCB4       0x0A08 // 10.8 - ADCB Interrupt 4
#define INT_ADCC_EVT    0x0A09 // 10.9 - ADCC Event Interrupt
#define INT_ADCC2       0x0A0A // 10.10 - ADCC Interrupt 2
#define INT_ADCC3       0x0A0B // 10.11 - ADCC Interrupt 3
#define INT_ADCC4       0x0A0C // 10.12 - ADCC Interrupt 4
#define INT_ADCD2       0x0A0D // 10.13 - ADCD Interrupt 2
#define INT_ADCD3       0x0A0E // 10.14 - ADCD Interrupt 3
#define INT_ADCD4       0x0A0F // 10.15 - ADCD Interrupt 4
#define INT_ADCCHECKINT 0x0A10 // 10.16 - ADC CHECK Interrupt

#define INT_CLA1_1   0x0B01 // 11.1 - CLA1 interrupts
#define INT_CLA1_2   0x0B02 // 11.2 - CLA2 interrupts
#define INT_CLA1_3   0x0B03 // 11.3 - CLA3 interrupts
#define INT_CLA1_4   0x0B04 // 11.4 - CLA4 interrupts
#define INT_CLA1_5   0x0B05 // 11.5 - CLA5 interrupts
#define INT_CLA1_6   0x0B06 // 11.6 - CLA6 interrupts
#define INT_CLA1_7   0x0B07 // 11.7 - CLA7 interrupts
#define INT_CLA1_8   0x0B08 // 11.8 - CLA8 interrupts
#define INT_MCANB    0x0B09 // 11.9 - MCANB interrupts
#define INT_ADCD_EVT 0x0B0A // 11.10 - ADCD EVT interrupts
#define INT_ADCH3    0x0B0B // 11.10 - ADCH interrupts 3
#define INT_ADCH4    0x0B0C // 11.11 - ADCH interrupts 4
#define INT_SDFM4DR1 0x0B0D // 11.13 - SDFM4DR1 Interrupt
#define INT_SDFM4DR2 0x0B0E // 11.14 - SDFM4DR2 Interrupt
#define INT_SDFM4DR3 0x0B0F // 11.15 - SDFM4DR3 Interrupt
#define INT_SDFM4DR4 0x0B10 // 11.16 - SDFM4DR4 Interrupt

#define INT_XINT3         0x0C01 // 12.1 - XINT3 Interrupt
#define INT_XINT4         0x0C02 // 12.2 - XINT4 Interrupt
#define INT_XINT5         0x0C03 // 12.3 - XINT5 Interrupt
#define INT_CLA1_CICP0    0x0C04 // 12.4 - CLA1_CIPC0 Interrupt
#define INT_CLA1_CICP1    0x0C05 // 12.5 - CLA1_CIPC1 Interrupt
#define INT_CLA1_CICP2    0x0C06 // 12.6 - CLA1_CIPC2 Interrupt
#define INT_CLA1_CICP3    0x0C07 // 12.7 - CLA1_CIPC3 Interrupt
#define INT_ADCH_EVT      0x0C08 // 12.8 - ADCH EVT Interrupt
#define INT_ADCF3         0x0C09 // 12.9 - ADCF Interrupt
#define INT_ECAP6_2       0x0C0A // 12.10 - HR ECAP6 Interrupt
#define INT_ECAP7_2       0x0C0B // 12.11 - HR ECAP7 Interrupt
#define INT_ADCH1         0x0C0C // 12.12 - ADCH Interrupt 1
#define INT_ADCH2         0x0C0D // 12.13 - ADCH Interrupt 2
#define INT_ADCF_EVT      0x0C0E // 12.14 - ADCF EVT Interrupt
#define INT_CLA_OVERFLOW  0x0C0F // 12.14 - CLA_OVERFLOW Interrupt
#define INT_CLA_UNDERFLOW 0x0C10 // 12.15 - CLA_UNDERFLOW Interrupt

#define INT_TIMER1 0x0D01
#define INT_TIMER2 0x0E01
#define INT_NMI    0x0F01

#endif // HW_INTS_H
